Reliability and Radiation Effects on Advanced CMOS Technologies



We investigate radiation effects on both SRAM- and Flash- based FPGAs.

SRAM-based FPGAs

We are studying the effects of ionizing radiation on devices as Spartan-3, Virtex, Virtex-II Pro and Virtex-4 designed by Xilinx.
We perform radiation tests on FPGAs using various radiation sources as heavy ions, alphas, neutrons, and x-rays. This permits us to get a complete characterization of the devices in all the possible radiation environments (both terrestrial and space). To achieve the static cross section of the FPGA we load a known pattern in the Device Under Test (DUT) Configuration Memory and periodically check for errors. The FPGAs are composed of different kind of elements (e.g. LUTs, Flip-Flops, Routing, etc..), and each one has different radiation sensitivity. We created a tool that permits to characterize the radiation sensitivity of each resource available inside the FPGA. Starting from this information we built up an analytical model to predict a circuit sensitivity just knowing the resources it needs to be implemented.
We test hardening-by-design techniques (such as TMR), exploring their effectiveness and performances when applied to different circuits. We study the impact of Configuration Memory’s errors accumulation on the reliability of the hardened designs.
We are focusing on the Multiple Bit Upset (MBU) as they could jeopardize the hardening techniques, for example simultaneously corrupting two TMR domains. We are gathering MBU events to correlate them with incident angle variations, particles energy and type, temperature, and Total Ionizing Dose (TID).


We are exploring Actel ProASIC3 Flash-based FPGA behavior when exposed to radiation. Thanks to Flash Configuration Memory, no upset may corrupt the circuit implemented. However, the device functionality may be affected by Single Event Transients (SETs). In particular we are characterizing the heavy ions induced SET widths and eventual variations due to total dose.




Each resource inside an FPGA features a different sensitivity to single event upsets.

Hardening using triplication can be uneffective with multiple errors in the configuration memory.