Advanced CMOS
Reliability and Radiation Effects on Advanced CMOS Technologies

 

 

[TUTORIAL UNDER CONSTRUCTION]

The spectacular evolution of CMOS technology, epitomized by Moore's famous law, has led to devices with feature size below one half of a tenth of nanometer. Unfortunately, scaling alone, i.e., the reduction of the physical size of the elemental devices, is no longer enough to sustain the performance growth and cost decrease that justify the development of a new process in economic terms. Innovations in material and device architecture are needed, also to overcome some of the fundamental physical limits which are being encountered along the road marked by Moore's law.

High-k oxides

Si02 has been the workhorse of the semiconductor industry since the introduction of the MOSFET. Scaling rules have caused the gate dielectric to become so thin that a significant tunnel current flows across it, leading to increase in power consumption and reliability issues. To overcome these problems, alternative materials with a higher dielectric constant have been used as gate oxide.

Silicon On Insulator

Silicon On Insulator technology offers distinct advantages over conventional bulk CMOS, in terms of performance, power consumption, and scalability.

Junction capacitance is reduced. Short channel effects are more under control, thanks to the superior electrostatic behavior of SOI MOSFETs.

There are two kinds of SOI devices, partially depleted and fully depleted.

Strain-inducing techniques

Another way to improve the performance of MOSFETs is to enhance the mobilty through strain-inducing techniques. By modifying the properties of the silicon lattice, it is indeed possible to augment the speed of the carriers, leading to higher-performing devices.

Resources

http://www.research.ibm.com/journal/rd50-45.html

 

 

QUICK FACTS

Intel introduced high-k gate oxides in its 45-nm technology.

IBM manufactures its processors with partially depleted SOI technology.