Soft Errors
Reliability and Radiation Effects on Advanced CMOS Technologies




Soft errors are considered by many the major threat to the reliability of digital computations. Soft errors, as opposed to hard errors, do not cause permanent damage to circuits, but simply loss of information. A zero stored in a memory may become a one and viceversa due to an impinging particle, an atmospheric neutron for instance. Soft errors are also known as Single Event Upsets (SEU) in the space community.

The mechanism responsible for the upset of a static memory cell can be described as follows: an ionizing particle strikes the drain of the switched-off NMOSFET in a cell, creating a track of electron-hole pairs. The reverse-biased pn junction collects part of the generated charge and changes its potential. If the potential change is large and long enough to overcome the restoring action of the PMOSFET and trigger the feedback, the stored value is corrupted.

A critical charge is needed to upset a cell, whose value depends on the supply voltage. The larger the supply voltage, the larger the critical charge.

Dynamic RAM has smaller sensitivy than SRAM, but upsets of these cells are possible as well.

Scaling Trends

As CMOS technology shrinks to lower and lower feature sizes, the impact of soft errors has greatly increased. Two contrasting factors balance, making the cross section per bit almost constant in the latest technology generations: on one hand, the reduction of the storage charge reduces the critical charge needed for the upset; on the other hand, the feature size reduction diminishes the chances of collecting charge, once this is generated by an ionizing particles.

Even though the cross section per bit remains more or less constant, the overall sensitivity increases due to the ever growing memory size used in advanced circuits.


IBM experiments in soft fails in computer electronics (1978-1994)




200 FIT/Mb is the reference reliability figure for soft erros in SRAMs